1. Field of the Invention
The subject invention relates generally to semiconductor wafer processing for integrated circuits and, more specifically, to interconnect processing for a semiconductor wafer.
2. Background Information
The process of manufacturing semiconductors or integrated circuits (commonly called ICs, or chips) typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit are formed on a single wafer. Generally, the process involves the creation of eight to twenty patterned layers on and into the substrate, ultimately forming the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface.
The first step in semiconductor manufacturing begins with production of a wafer—a thin round slice of a semiconductor material, usually silicon. In this process, purified polycrystalline silicon is heated to molten liquid. A seed of solid silicon is used to form a single crystal ingot. The crystal ingot is then ground to a uniform diameter and a diamond saw blade cuts the ingot into thin wafers. The wafer is processed through a series of machines, where it is ground smooth and chemically polished to a mirror-like luster. The wafer is then ready to be sent to the wafer fabrication area where it is used as the starting material for manufacturing integrated circuits.
The wafer fabrication facility is where the integrated circuit is formed in and on the wafer. The fabrication process, which takes place in a clean room, involves a series of principle steps described below. Typically, it takes from about ten to thirty days to complete the fabrication process.
A first step in the wafer fabrication process is thermal oxidation or deposition. Wafers are pre-cleaned using high purity, low particle chemicals. The silicon wafer is heated and exposed to ultra-pure oxygen in a diffusion furnace under carefully controlled conditions forming a silicon dioxide film of uniform thickness on the surface of the wafer. The wafer is now ready for masking prior to etching.
Masking is used to protect one area of the wafer while working on another area. This process is referred to as photolithography or photo-masking. A photoresist or light-sensitive film is applied to the wafer, giving it characteristics similar to a piece of photographic paper. A photo aligner aligns the wafer to a mask having a particular pattern thereon. An intense light is then projected through the mask and through a series of reducing lenses, exposing the photoresist with the mask pattern.
The wafer is then developed after exposure. Particularly, the wafer is processed such that the areas of the photoresist that have been exposed to light are either removed (as in the case of positive tone photoresist) or remain (as in the case of negative tone photoresist, in which case those areas not exposed are removed). The wafer is then baked to harden the remaining photoresist pattern. The wafer is then exposed to a chemical solution or plasma (gas discharge) so that areas not covered by the hardened photoresist are etched away. The photoresist is then removed using additional chemicals or plasma. The wafer is then inspected to ensure that image transfer from the mask to the top layer is correct. The wafer is then ready for doping.
Atoms with one less electron than silicon (such as boron), or one more electron than silicon (such as phosphorous) are introduced into the areas exposed by the etch process in order to alter the electrical characteristics of the silicon. These areas are called either P-type (boron) or N-type (phosphorous) to reflect their conducting characteristics.
The thermal oxidation, masking etching, and doping steps are typically repeated several times until the last “front end” layer is completed (i.e. all active devices have been formed). The wafer is then ready for dielectric deposition and metalization.
Following completion of the front end, “back end” processing is started. Back end processing includes steps from the contact layer through completion of the wafer but prior to electrical test. In back end processing, the individual devices formed as indicated above are interconnected using what are known as interconnects. The interconnects are formed in what is known as an interconnect layer. Current semiconductor fabrication includes as many as three interconnect layers separated by dielectric layers.
An interconnect is a metal conductor line that connects elements of the integrated circuit. These lines are delineated in dielectrics that isolate the interconnects from each other. Interconnects may be formed by several processes. In one process, a series of metal depositions and patterning steps of dielectric films (insulators) are provided. This is known as dielectric deposition and metalization. In another process, the interconnects are formed by means of lithography and etching (i.e. metal etching). In yet another process, known as a damascene process, interconnects are formed by lithography, deposition and chemical mechanical polishing or planarization (CMP). Particularly, an interconnect pattern is first lithographically defined utilizing a mask in the layer of dielectric. Then metal such as aluminum or copper is deposited to fill the resulting trenches. The excess metal is then removed by means of CMP.
After the last metal layer is patterned, a final dielectric layer (passivation) is deposited to protect the circuit from damage and contamination. Openings are etched in this film to allow access to the top layer of metal by electrical probes and wire bonds. An automatic, computer-driven electrical test system then checks the functionality of each chip on the wafer. Chips that do not pass the test are marked for rejection.
Thereafter, the wafer is cut into single chips. The functional chips are visually inspected under a microscope before packaging. The chip is then assembled into a package that provides the contact leads for the chip. A wire-bonding machine then attaches wires, a fraction of the width of a human hair, to the leads of the package. Encapsulated with a plastic coating for protection, the chip is tested again prior to delivery to the customer. Alternatively, the chip is assembled in a ceramic package for certain military applications.
In the formation of interconnects, several problems currently exist. One problem is varying metal density of a back end layer. Varying metal density of a back end layer will produce varying interconnect thickness due to CMP processing. In general, interconnects that are crowded together will have similar thickness values. This variation will affect interconnect resistance and capacitance, and thus circuit behavior.
With respect to a damascene copper process, interconnect thickness is a strong function of metal density. Since the metal density in a real chip is often highly non-uniform, the CMP copper process often results in a large amount of metal thickness variations.
One solution to the variation in interconnect thickness is to provide circuit design rules that limit metal density variation in order to keep CMP-induced thickness variations within acceptable limits. This solution, however, is not necessarily practical due to the complexity of current integrated circuit components. Moreover, design rules are difficult to develop and difficult to interpret.
However, in order to attempt to meet the design rule metal density requirements, dummy metals are needed placed in blank areas. Dummy metal placement will increase the layout complexity and overall design time. Moreover, because of the random nature of interconnect routings, metal density variation will still exist even with placement of dummy metals.
According to one aspect, what is therefore needed in view of the above, is a system, method and/or apparatus that provides an almost constant metal pattern density for interconnects and/or an interconnect layer or layers in a semiconductor wafer for integrated circuit manufacture.
Another problem with the interconnect process concerns the masks used to perform interconnect photolithography processing. Because of the complexity of current interconnect routing in modern integrated circuit technology, interconnect layer masks are becoming prohibitively expensive.
One solution to prohibitively expensive interconnect processing masks is to provide multi-purpose masks where one mask can be used for multiple products or layers. This solution, however, is not necessarily practical. Particularly, such multi-purpose masks are still relatively expensive and error-prone. Another solution is to direct-write a pattern onto the whole wafer utilizing a direct-write system. This solution is, as well, impractical. Direct-write systems are inherently slow and thus provide low throughput.
According to another aspect, what is therefore needed in view of the above, is a system, method and/or apparatus that provides interconnects and/or an interconnect layer or layers in a semiconductor wafer having an almost constant metal density.